Numerous improvements within integrated circuit technology have been made in recent years. Example improvements include the provision of an increased number of devices, such as transistors, on a single semiconductor die. Further, technological advancements have reduced the overall size of individual semiconductor dies in general. Such improvements provide processing devices which can operate at increased speeds as well as memory devices which are capable of storing increased amounts of data within a single device.
The improvements have not been limited to the semiconductor dies themselves. In particular, numerous improvements have been made in packaging technologies for semiconductor dies. Chip scale packages (CSP) have been developed to provide improved package arrangements for integrated circuit devices. Exemplary chip scale packages include ball-grid array (BGA) packages and fine pitch ball-grid (FBGA) packages.
In BGA and FBGA packaging techniques, a fabricated semiconductor die such as a dynamic random-access memory chip is adhered by tape or other adhesive to a surface of a printed circuit board (PCB) or other substrate. The substrate typically has a plurality of conductive traces formed upon an opposing surface from the adhered semiconductor die. The printed circuit board additionally includes a plurality of solder balls formed in electrical connection with respective ones of the conductive traces. Integrated circuitry of the semiconductor die is coupled with the traces and conductive bumps. Such can be accomplished using wire bonding connections in an exemplary configuration.
Chip scale packaging technology provides numerous improvements over conventional leadframe-type semiconductor packaging technology. For example, chip scale packages provide semiconductor die packages having improved electrical performance (e.g., reduced parasitic capacitance and inductance). In addition, such packages provide shorter distances intermediate bond pads of the semiconductor die and the conductive bumps configured to couple with circuitry external of the integrated circuit package. Such improves the speed of performance of the integrated circuit package.
In addition to performance improvements, chip scale packages provide maximized usage of substrate real estate. More specifically, chip scale packages have a footprint which is only slightly larger than the size of the semiconductor die. In some conventional packaging technologies, the semiconductor die comprises only approximately 25 percent of the package area and the remainder comprises an encapsulating epoxy. Further, chip scale packages provide an integrated circuit package having an overall height which is smaller than conventional semiconductor device packages. For example, exemplary chip scale packages have a height of approximately 1.2 millimeters or less for use in specialized applications.
However, a distinct disadvantage exists with conventional chip scale packages. In particular, a first surface of the semiconductor die is typically affixed to the printed circuit board or other substrate of the package. The opposing side of the semiconductor die is exposed and is subject to damage. In particular, such integrated circuit packages individually having an exposed semiconductor die surface are highly vulnerable to damage during testing or other handling of the packages. As a result, a comparatively lower yield of chip scale packages has been observed during test and board assembly.
Therefore, a need exists to provide improved structures and methodologies for packaging semiconductor dies.